[sv-bc] SystemVerilog 3.1a Draft 5 is available!

Subject: [sv-bc] SystemVerilog 3.1a Draft 5 is available!
From: David W. Smith (dwsmith@synopsys.com)
Date: Fri Feb 27 2004 - 16:43:55 PST

• Next message: Vassilios.Gerousis@infineon.com: "[sv-bc] LRM Milestones dates and Committee Voting"
• Previous message: Vassilios.Gerousis@infineon.com: "[sv-bc] FW: UPDATED: SystemVerilog3.1 interfaces: Synthesizing using modp orts"
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

Greetings,

SystemVerilog 3.1a Draft 5 is now available. All change items have been implemented and verified with the exception of the Index.
Within the next week the Index will be posted on the site as well.

To access the LRM please use one of the following two URLs:

http://171.64.100.61/sv/SystemVerilog_3.1a_draft5.pdf

Or

http://www.eda.org/sv/SystemVerilog_3.1a_draft5.pdf

The first one should be more accessible and is faster for download.

Regards

David

David W. Smith
Synopsys Scientist

Synopsys, Inc.
Synopsys Technology Park
2025 NW Cornelius Pass Road
Hillsboro, OR 97124

Voice: 503.547.6467
Main: 503.547.6000
FAX: 503.547.6906
Email: <mailto:david.smith@synopsys.com> david.smith@synopsys.com
 <http://www.synopsys.com> http://www.synopsys.com

• Next message: Vassilios.Gerousis@infineon.com: "[sv-bc] LRM Milestones dates and Committee Voting"
• Previous message: Vassilios.Gerousis@infineon.com: "[sv-bc] FW: UPDATED: SystemVerilog3.1 interfaces: Synthesizing using modp orts"
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

This archive was generated by hypermail 2b28 : Fri Feb 27 2004 - 17:47:32 PST