Subject: [sv-bc] review items in System Verilog 3.1a draft 4
From: Jonathan Bradford;Freiburg (bradford@micronas.com)
Date: Wed Feb 11 2004 - 01:39:06 PST
Here are some review items in System Verilog 3.1a draft 4 :-
p.77 ) 7.20 Set Membership
The inside operator uses the equality (===) operator ...
Select a font to indicate == or === clearly. (2 x = or 3 x =).
p.134) 12.4.3 Set Membership + p.77) 7.20 Set Membership
It is important to note that the inside operator is bidirectional,
...
+
the don't care is unidirectional.
Both the unidirectional and bidirectional significance needs to be
described in each chapter,
rather than splitting one to each. Otherwise they seem to contradict.
That they describe different aspects of the inside statement is not
obvious when so split.
p.150) 12.10 In-line random variable control
a.randomize(); // random variables: x, ystate variables: v, w
->
a.randomize(); // random variables: x, y state variables: v, w
Missing space between random and state variable comment on those 4
example lines.
p.113) 11.3 Overview + p.166) 13.2 Semaphores + p.168) 13.3 Mailboxes +
p.99) 9.9 Fine grain process control
A common convention is to capitalize the first letter of the class
name, ...
+
semaphore smTx;
+
mailbox mbxRcv;
+
class process;
Built in classes not complying with the convention. In appendix D the
class List is defined, with first letter capitalised.
Does the non-capitalisation imply the builtin class cannot be overridden
(nor derived from in the case of process),
if so extend convention description.
p.262) 18.1 Introduction + p.267) 18.4 Top level instance
Removal of $root global declaration space ...
+
The name $root is added to ...
Apparent contradiction of $root.
p.271) 18.8 Port declarations
a port can be a declaration of a net, an interface, an event, or a
variable of any type including an array, structure or union.
What about class or object or handle or queue etc ? Define what a port
cannot be.
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