Re: [sv-bc] Question regarding 2-state and 4-state members in packed structs


Subject: Re: [sv-bc] Question regarding 2-state and 4-state members in packed structs
From: Dave Rich (David.Rich@synopsys.com)
Date: Tue Feb 10 2004 - 14:52:32 PST


Nikhil,

This means the packed structure as a whole is treated as 4-state.
Writing or reading to a 2-state member is cast to a 2-state value. See
more answers below

Rishiyur S. Nikhil wrote:

> Dear all,
>
> (Apologies for being so pesky today!)
>
> I'm trying to understand the following statement in Section 3.11:
>
> "If any data type within a packed structure is 4-state, the whole
> structure is treated as 4-state. Any 2-state members are
> converted as if cast."
>
> Here are some specific questions. Suppose we have:
>
> struct packed {
> int a; // 2-state
> logic b; // 4-state
> logic c; // 4-state
> } x;
>
> Suppose we have:
>
> x.a = ... some 4-state value ...; // (1)
>
> ... = ... x.a ...; // (2)
>
> In (1), does the 4-state value get cast to a 2-state value before the
> assignment into x.a?

Yes. writing to a 2-state member is cast to a 2-state value

>
> In (2), is it possible to read out a 4-state value from x.a?
>
No. Reading from a 2-state member is cast to a 2-state value

>
> Or, suppose we have:
>
> x = { a:0, b:1'bx, c:1'bz};
>
> and then we do a shift operation to shift the 4-state values into the
> 2-state member:
>
> x = x << 2;
>
> Do 4-state values get shifted into the 2-state member?

Yes. The struct as a whole is treated as 4-state

> Or do they get cast to a 2-state value before shifting in?

No. The struct as a whole is treated as 4-state

> What do we get when we now read x.a?

Reading from a 2-state member is cast to a 2-state value

>
> Thanks for any clarifications you can provide,
> (i.e., what's the right way to think about mixed 2-state/4-state
> packed structs,
> from whence the answers to all these questions become obvious?)
>
> Nikhil
>
>
>

-- 
--
David.Rich@Synopsys.com
Technical Marketing Consultant and/or
Principal Product Engineer
http://www.SystemVerilog.org
tele:  650-584-4026
cell:  510-589-2625



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