[sv-bc] SystemVerilog 3.1a Draft 4

Subject: [sv-bc] SystemVerilog 3.1a Draft 4
From: David W. Smith (dwsmith@synopsys.com)
Date: Sun Feb 01 2004 - 21:49:57 PST

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Greetings,

Draft 4 of the SystemVerilog 3.1a has been posted to www.eda.org/sv. All changes marked in the LRM change list are complete except
for the changes to Section H (SystemVerilog Concurrent Assertions Semantics). An additional PDF file will be generated later this
week and be posted on the web site.

Regards

David

David W. Smith

Synopsys Scientist

Synopsys, Inc.

Synopsys Technology Park

2025 NW Cornelius Pass Road

Hillsboro, OR 97124

Voice: 503.547.6467

Main: 503.547.6000

FAX: 503.547.6906

Email: david.smith@synopsys.com

http://www.synopsys.com <http://www.synopsys.com/>

• Next message: Karen Pieper: "[sv-bc] Time literal question"
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