RE: [sv-bc] SystemVerilog 3.1a Draft 3 - Stu-note on enumerated names/labels


Subject: RE: [sv-bc] SystemVerilog 3.1a Draft 3 - Stu-note on enumerated names/labels
From: Peter Flake (Peter.Flake@synopsys.com)
Date: Sun Jan 25 2004 - 16:19:15 PST


Stu,

It was pointed out that the SystemSim use of %s was inconsistent with
V2001, which requires the register value to be interpreted as ASCII.
The proposed alternative was %n, which makes sense. However this was later
withdrawn in favour of the .name method at the BC.

BTW I prefer "name" too, though not very strongly.

Peter.

At 23:38 23/01/2004 -0800, Stuart Sutherland wrote:

>To follow-up on Cliff's comments:
>
>I am fine with calling the enumerated values "names" instead of "labels",
>though personally I think "labels" is a more appropriate term. The
>important thing is that the LRM terminology be consistent, which it is not
>right now.
>
>Using the .name method to print a enum value by name is already in the LRM,
>starting with 3.1 (section 3.10.5.6).
>
>Printing an enum value by name using %s was a feature of the Co-design
>SystemSim simulator for a long time, but disappeared in the last couple of
>releases. Using %s was shown by example in a number of old Co-design
>presentations and training materials. However, using %s with enumerated
>types was not documented in the Co-design SUPERLOG manual, the donated
>SUPERLOG ESS manual or in the SV 3.0 LRM.
>
>Personally, I think it is intuitive to print enumerated type variables by
>name using %s, and by value using a numeric format such as %d, %h or %b. I
>propose we add this to SV 3.1a.
>
>Stu
>
>~~~~~~~~~~~~~~~~~~~~~~~~~
>Stuart Sutherland
>stuart@sutherland-hdl.com
>503-692-0898
>
> > -----Original Message-----
> > From: owner-sv-bc@server.eda.org
> > [mailto:owner-sv-bc@server.eda.org] On Behalf Of Clifford E. Cummings
> > Sent: Friday, January 23, 2004 6:02 PM
> > To: sv-bc@server.eda.org
> > Subject: [sv-bc] SystemVerilog 3.1a Draft 3 - Stu-note on
> > enumerated names/labels
> >
> > Hi, All -
> >
> > In section 3.10.2 on page 18 of the SV 3.1a Draft 3 LRM, Stu
> > points out
> > that enum names/labels should be documented consistently
> > throughout the
> > LRM. I agree.
> >
> > Stu prefers "label."
> >
> > I prefer "name" for two reasons:
> >
> > (1) We have already added labels to SV (section 8.8)
> >
> > (2) ModelSim and VCS have already implemented a ".name" modifier to
> > $display enumerated names. Example
> >
> > enum {a, b, c} xxx;
> > $display ("%s", xxx.name); // .name required to see the string name
> >
> > This works for both VCS and ModelSim to display the
> > enumerated names. I
> > think someone said this came from a PLI enhancement which was
> > defined for
> > handling enumerated names???
> >
> > Whatever we decide, I don't think we have documented how to $display
> > enumerated names. We should choose something like:
> >
> > $display ("%s", xxx); // name is shown automatically.
> > $display ("%s", xxx.name); // .name required but then what
> > should be shown
> > for just xxx? Right now it comes up blank for both simulators.
> > $display ("%s", xxx.label); // .label required but same
> > question as above.
> >
> > Thoughts?
> >
> > Regards - Cliff
> >
> >
> > ----------------------------------------------------
> > Cliff Cummings - Sunburst Design, Inc.
> > 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> > Phone: 503-641-8446 / FAX: 503-641-8486
> > cliffc@sunburst-design.com / www.sunburst-design.com
> > Expert Verilog, SystemVerilog, Synthesis and Verification Training
> >
> >
> >



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