Subject: [sv-bc] RE: [sv-cc] Draft 2 of SystemVerilog LRM
From: Warmke, Doug (doug_warmke@mentorg.com)
Date: Tue Dec 16 2003 - 18:23:47 PST
SV-BC,
I reviewed the changes for item LRM-79 (multi-dimensional array support
in $readmem/$writemem).
The following jumped out at me:
Why are we treating unpacked dimensions so carefully?
The original text in this part of the SV LRM had the following:
$readmemb and $readmemh are extended to unpacked arrays of packed data,
associative arrays of packed
data, and dynamic arrays of packed data. In such cases, the system tasks
treat each packed element as the vector
equivalent and perform the normal operation.
The text above appears ideal for enum types and packed struct types.
But in hindsight, it seems more practical to treat packed array
dimensions identically
to unpacked array dimensions when it comes to:
- file format
- system task arguments
I propose we open an erratum and make the following changes to
sections 23.14, 23.16, and 23.17 of SV3.1a LRM, draft2:
Section 23.14:
1. Add the following sentence at the end of the paragraph above:
However, note that multidimensional packed arrays are an exception to
this rule.
They are discussed in section 23.16 (File format considerations for
multidimensional arrays)
Section 23.16:
2. Change all uses of the phrase "unpacked array" to be simply "array".
3. Change the first sentence to read:
In SystemVerilog, $readmemb, $readmemh, $writememb, and $writememh can
work
with multi-dimensional arrays, both packed and unpacked.
4. After the "Note that the diagram would be identical..." sentence and
subsequent
example with "reg [31:0] mem [2:0][0:4][8:5];", add the following:
Further, note that the diagram would be identical if one or more of the
unpacked
array dimensions was changed to an equivalent packed dimension:
reg [8:5][31:0] mem [2:0][0:4];
Section 23.17:
5. Change all uses of the phrase "unpacked array" to be simply "array".
I will be on vacation until early January, but available on email to
discuss this issue.
If needed, I can call in for a committee meeting to present this
proposal verbally
and make a motion to pass it. But please email me the conference call
details -
I won't be able to look them up easily!
Thanks and regards,
Doug
-----Original Message-----
From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On Behalf Of
David W. Smith
Sent: Monday, December 15, 2003 5:06 PM
To: sv-ac@eda.org; sv-bc@eda.org; sv-cc@eda.org; sv-ec@eda.org
Subject: [sv-cc] Draft 2 of SystemVerilog LRM
Greetings,
The Draft 2 version of the LRM is now available at:
http://www.eda.org/sv/SystemVerilog_3.1a_draft2.pdf
<http://www.eda.org/sv/SystemVerilog_3.1a_draft2.pdf>
Stu has done a wonderful job of editing all of the changes into the LRM.
Thank you Stu for you continued efforts.
We will do a Draft 3 as soon as we have the final changes from all of
the committees (hopefully later this week).
Regards
David
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