Subject: AW: [sv-bc] SV-BC issues from thomas Kruse
From: Thomas.Kruse@infineon.com
Date: Fri Dec 12 2003 - 00:34:13 PST
Hi Dave,
I aggree with Shalom. The SV LRM is not a VHDL LRM. If there
is a specific term in SV LRM, it should be defined properly
there.
Regards,
Thomas
-----Ursprüngliche Nachricht-----
Von: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] Im Auftrag von
Shalom.Bresticker@motorola.com
Gesendet: Donnerstag, 11. Dezember 2003 21:37
An: Dave Rich
Cc: sv-bc@eda.org
Betreff: Re: [sv-bc] SV-BC issues from thomas Kruse
Dave,
While 'signal' is indeed used throughout the IEEE Verilog LRM, it is not
defined anywhere, and I indeed disagree with your definition. I would
loosely define it as a general term to denote a net or variable, although
that is a
little simplistic.
And although I do not know VHDL, I seem to remember that the term has a
specific meaning in the VHDL LRM which is different from its meaning in
the Verilog LRM.
Shalom
On Thu, 11 Dec 2003, Dave Rich wrote:
> 'signal' is used throughout the IEEE 1364-2001 spec, and is used with
> the same meaning in SV and VHDL. (Any identifier whose value change
> creates an event, i.e. signals an event)
> Shalom.Bresticker@motorola.com wrote:
>
> >In 85, Thomas wrote:
> >
> > What is the definition of 'signal'?
> > What is the definition of 'scalar'?
> >
> >'scalar' is indeed defined in IEEE 1364-2001 in section 3.3: "A net
> >or reg declaration without a range specification shall be considered
> >1 bit wide and is known as a scalar."
> >
> >However, 'signal' is not defined.
-- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
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