Subject: [sv-bc] Enhancement Request: 2-state wildcard for case-items (in case, casez, and casex)
From: Karen Pieper (Karen.Pieper@synopsys.com)
Date: Sat Dec 06 2003 - 18:26:16 PST
The following mail is from Mike Turpin of Arm. It bounced because he is
not a member of the
mailing list.
Karen
<Mail from Mike Turpin>
Hi,
I just read an EETimes article on SystemVerilog and this prompted me to
make an enhancement request, to allow a new 2-state wildcard symbol for
case-items (maybe "*").
Many designers use X in casex-items or Z/? in casez-items as wildcards, as
they cannot use normal case statements (there's no wildcard here). The
designers intent is normally to match incoming 2-state (0 or 1)
combinations - but the casex/casez wildcards also match incoming X's (which
can be dangerous).
I've attached a paper I've written on X-issues in Verilog - which won an
award at Boston SNUG 2003. One of it's key recommendations is that
X-propagation in case-defaults has to be more sensible than optimistic
X-termination. Another argues against ever using casex and only using casez
with care.
Here's an example. You need to code a case statement that's got a 32-bit
case item and you only want to specify a few combinations as assigning 1'b1
- with the rest assigning 1'b0. Using a standard case-statement, the 2^32
combinations means that it's only practical to use the default to assign 0
rather than X - which could cause simulation vs synthesis differences (if
don't-care X's get minimized to a specific case-item that would assign
1'b1, then the netlist simulation differs to the RTL simulation).
With a "*" 2-state wildcard you could have separate 2-state and 4-state
case defaults, e.g.:
case (sel)
... // case-items assigning X
32'h****_****: o1 = 1'b0; // New wildcard allows 2-state default
default: o1 = 1'bX; // X-propagation
endcase
This 2-state wildcard would also allow more obvious priority encoders in a
case statement, e.g.:
case ({w1, w2, w3})
3'b1**: o2 = i1; // w1 has highest priority
3'b01*: o2 = i2;
3'b001: o2 = i3;
3'b000: o2 = 2'b00;
default: o2 = 2'bXX; // X-propagation
endcase
This above form avoids the use of nested if-statements (which are dangerous
as they handle X's optimistically as 0).
I'd like to propose a 2-state wildcard for case, casez and casex - with
some recommendations on it's use over the existing wildcards. I'd
appreciate any feedback on this.
One last thing, I'm not sure why the SystemVerilog 3.1a LRM states that you
don't need to specify a default when you use unique/priority prefixes. I'm
not sure of the simulation semantics for these, but it would be good to see
a recommendation to enable X propagation.
Regards,
Mike
_____________________________________________________________
Mike Turpin Tel: +44-1223-400459
Principal Verification Engineer Eml: Mike.Turpin@arm.com
CPU Verification
ARM, Cambridge, UK
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