[sv-bc] New errata - wildcard equality
Subject: [sv-bc] New errata - wildcard equality
From: Dave Rich (David.Rich@synopsys.com)
Date: Sat Nov 15 2003 - 15:02:51 PST
I put this as a proposal to both the EC and BC.
To be useful for design RTL, the wildcard operator must propagate Xs
and match casez semantics. The original VERA donation did not have this
as a consideration for design.
Remove the striked text in table 7-1
a equals b, X and Z values
act as wild cards
a not equals b, X and Z
values act as wild cards
Remove the striked text in section 7.5 and add the text in blue
The wild equality operator (=?=) and inequality operator (!?=) treat X and Z values in a given bit
position as a
wildcard.
The three types of equality (and inequality) operators in SystemVerilog
behave differently when their operands
contain unknown values (X or Z). The == and != operators result in X if
any of their operands contains an X or
Z. The === and !== check the 4-state explicitly, therefore, X and Z
values shall either match or mismatch,
never resulting in X. The =?= and !?= operators treat
X or Z as wild cards that match any value,
thus, they too
never will not result in X when
matched with a Z value.
--
--
David.Rich@Synopsys.com
Technical Marketing Consultant
http://www.SystemVerilog.org
tele: 650-584-4026
cell: 510-589-2625
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