Subject: [sv-bc] keywords as identifiers
From: Hermann.Ilmberger@Infineon.Com
Date: Thu Nov 13 2003 - 06:38:59 PST
SystemVerilog at some places allows keywords to be used as identifier:
function new();
this.x = 23;
super.new(5);
Nothing is defined in the grammar whether "new" is allowed here.
implicit_class_handle ::= [ this. ] | [ super. ]
starts to define the places, where "this" and "super" are allowed.
The following is the only rule that uses implicit_class_handle:
primary ::=
...
| implicit_class_handle hierarchical_identifier { [ expression ] } [ [
range_expression ] ] [ . method_identifier { attribute_instance } [ (
expression { , expression } ) ] ]
However, it seems that this does not cover things like:
this.super.x
this.method(23)
this.x = 23;
So "this", "super" and "new" are intended to be used at more places
than the grammar allows. What should we do here?
-Hermann
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