Subject: [sv-bc] Connecting arrays of interface instances using a modport -- slice syntax needs clarification
From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Sat Nov 08 2003 - 17:06:33 PST
The LRM needs clarification, perhaps via an example, about how
to refer to a slice of an array of interface instances when
the slice is connected using a modport.
For example, it seems clear that an entire array of 'server'
instances, each of which is to be connected using the same
kind of 'slave' modport, would be denoted by
servers.slave
When a bit-select or part-select is used, however, does it precede
or follow the modport identifier? I think it would be consistent
with the rest of Verilog if it were to follow the modport identifier,
for example,
servers.master[0], servers.slave[1:7]
or, in context,
localparam P = 8 ;
interface IFC (clk ) ;
...
modport master( input clk, input a, ... ) ;
modport slave( input clk, output a, ... ) ;
...
endinterface
module top( input clk ) ;
IFC servers [0:P-1] ( clk ) ;
bottom bot ( servers.master[0], servers.slave[1:P-1] ) ;
endmodule
module bottom ( IFC.master initiator , IFC.slave targets [1:P-1] ) ;
generate for (genvar i = 1 ; i < P ; i++) begin : GENFOR
assign targets[i].a = ... ;
...
end
...
endmodule
-- Brad
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