Subject: [sv-bc] Erratta or simple proposal for task, function, property,sequence arguments.
From: Adam Krolnik (krolnik@lsil.com)
Date: Thu Nov 06 2003 - 07:28:43 PST
Good morning all;
SV 3.1 added the shorthand ability to named port connections to only
mention the name of the port. The net name would be assumed to match
the port name. E.g
DFF flop1 (.q(delay_sig),
.d(sig),
.clk, // Connect net 'clk' to port 'clk'
.rst_n // Connect net 'rst_n' to port 'rst_n'
);
I propose that the committee overlooked adding this shorthand ability for
the task, function, property and sequence argument lists. The IEEE committee
included the named connection ability to tasks and functions to be symmetric
with port connections.
The BNF changes include adding the shorthand to the list_of_arguments,
list_of_constant_arguments and actual_arg_list productions. It would
also require creating a separate production for the new class call as
it uses the list_of_arguments production. Note, constant functions could
use this too, though the function argument would only be able to match a
genvar identifier.
Proposal:
WAS:
list_of_arguments ::=
[ expression ] { , [ expression ] }
| . identifier ( [ expression ] ) { , . identifier ( [ expression ] ) }
list_of_constant_arguments ::=
[ constant_expression ] { , [ constant_expression ] }
| . identifier ( [ constant_expression ] ) { , . identifier ( [ constant_expression ]
) }
actual_arg_list ::=
( actual_arg_expr { , actual_arg_expr } )
| ( . formal_identifier ( actual_arg_expr ) { , . formal_identifier ( actual_arg_expr ) } )
blocking_assignment ::=
variable_lvalue = delay_or_event_control expression
| hierarchical_variable_identifier = new [ constant_expression ] [ (
variable_identifier ) ]
| class_identifier [ parameter_value_assignment ] = new [ ( list_of_arguments ) ]
Proposed:
-- Make parenthesis expression optional.
list_of_arguments ::=
[ expression ] { , [ expression ] }
| . identifier [ ( [ expression ] ) ] { , . identifier [ ( [ expression ] ) ] }
-- Make parenthesis expression optional.
list_of_constant_arguments ::=
[ constant_expression ] { , [ constant_expression ] }
| . identifier [ ( [ constant_expression ] )] { , . identifier [ ( [
constant_expression ] ) ] }
-- Make parenthesis expression optional.
actual_arg_list ::=
( actual_arg_expr { , actual_arg_expr } )
| ( . formal_identifier [ ( actual_arg_expr ) ] { , . formal_identifier
[ ( actual_arg_expr ) ] } )
-- Replace list_of_arguments with list_of_class_arguments.
blocking_assignment ::=
variable_lvalue = delay_or_event_control expression
| hierarchical_variable_identifier = new [ constant_expression ] [ (
variable_identifier ) ]
| class_identifier [ parameter_value_assignment ] = new [ ( list_of_class_arguments ) ]
-- Add this new production.
list_of_class_arguments ::=
[ expression ] { , [ expression ] }
| . identifier ( [ expression ] ) { , . identifier ( [ expression ] ) }
To section 10.5.4 (Argument passing by name) do the following:
Was:
SystemVerilog allows arguments to be tasks and functions to be passed by name as well as
by position. This allows specifying non-consecutive default arguments and easily
specifying the argument to be passed at the call.
Proposed:
SystemVerilog allows arguments to be tasks and functions to be passed by name as well as
by position. This allows specifying non-consecutive default arguments and easily
specifying the argument to be passed at the call.
Named arguments specify the formal argument (as .name) to be associated with an optional
passed argument, specified in parenthesis. Named arguments without a specific argument
passed will implicitly pass a variable from the current scope with the same name and
matching type as the formal argument to the task or function. Mismatches in the type
shall be an error.
Named arguments allow for
18.7.3 Instantiation using implicit .name port connections SystemVerilog adds the
capability to implicitly instantiate ports using a .name syntax if the instance-port
name and size match the connecting variable-port name and size. This enhancement
eliminates the requirement to list a port name twice when the port name and signal name
are the same, while still listing all of the ports of the instantiated module for
documentation purposes.
To section 17.6 (Declaring sequences) change the following:
WAS:
Formal arguments can be optionally specified. A formal argument is untyped, and is used
for syntactic replacement of a name or an expression in the sequence. An actual argument
can replace an:
Formal arguments can be optionally specified. A formal argument is untyped, and is used
for syntactic replacement of a name or an expression in the sequence.
Argument passing can be by position or named argument passing (as .name). Named
arguments associates the formal argument with an optional passed argument specified in
parenthesis. Named arguments without a specific argument will implicitly pass a variable
from the current scope with the same name. Arguments do not need to be passed for
formal arguments that have a default value. An actual argument shall be:
To section 17.10 (The property definition) add the following:
WAS:
A property is declared with optional formal arguments, as in a sequence declaration.
When a property is instantiated, actual arguments can be passed to the property. The
property gets expanded with the actual arguments by replacing the formal arguments with
the actual arguments. The semantic checks are performed to ensure that the expanded
property with the actual arguments is legal.
Proposed:
Formal arguments can be optionally specified as in a sequence declaration. A formal
argument is untyped, and is used for syntactic replacement of a name or an expression in
the sequence.
Argument passing can be by position or named argument passing (as .name). Named
arguments associates the formal argument with an optional passed argument specified in
parenthesis. Named arguments without a specific argument will implicitly pass a variable
from the current scope with the same name. Arguments do not need to be passed for
formal arguments that have a default value. The semantic checks are performed to ensure
that the expanded property with the actual arguments is legal.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
Co-author "Assertion Based Design"
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