[sv-bc] IEEE SystemVerilog (1800) Working Group Meeting

From: Brophy, Dennis <dennis_brophy@mentor.com>
Date: Wed Feb 11 2015 - 16:40:28 PST
Chair Karen Pieper has invited you to the SystemVerilog standardization re-start meeting.  Please RSVP by accepting or declining this meeting invitation or with a reply email back to me.  Each subcommittee is offered a 30-minute slot to present their findings on next steps in standardization.

Please note: We need your RSVP as the meeting will be held in a room that can accommodate up to 28 people.  We are planning for 15 to attend in person.  So there should be room for everyone.  For those unable to attend in person but would like to participate, we will provide a WebEx & audio connection.  Remember, attendance in person offers the best quality of interaction and we apologize in advance if you experience interaction issues by not attending in person.

Cadence Design Systems has graciously accepted to host the meeting.  Please share any dietary restrictions you may have in order to accommodate your needs.

Agenda:
http://www.eda.org/twiki/bin/view.cgi/P1800/P1800Agendas

  1.  Welcome & Introductions (9am)
  2.  BC Report 9:15
  3.  EC Report 9:45
  4.  CC Report 10:15
        -- break -- (10:45)
  5. DC Report 11:00
        -- lunch -- (11:30)
  6. AC Report 11:45
  7. Roundtable Discussion 12:15
         - Go/No go on action to move forward
  8. Conclude 1:00pm

Teleconference Information:
1. Dial-In:
    - UNITED STATES: 800-637-5822 (free with Skype)
    - UNITED STATES (Toll): +1-917-210-2607

2. Enter Access Code: 6850893

Click here for a list of global toll-free numbers <http://conf.cfer.com/?startview=gos&spid=154&ac=6850893&an=8006375822&login=true>

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Meeting number: 319 765 573
Meeting password: 1800


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Received on Wed Feb 11 16:40:57 2015

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