[sv-bc] RE: Clarification for `1 usage in unpacked array concatenation

The operands in an unpacked array concatenation are self-determined, just like Verilog integral concatenation. So 1'b1 should be the result. Assignment patterns are context determined. This is one of the key distinctions between the two forms.

Dave


From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Goel, Rohit (Noida MED RTLC Synthesis)
Sent: Wednesday, July 23, 2014 3:49 AM
To: sv-bc@eda.org
Subject: [sv-bc] Clarification for `1 usage in unpacked array concatenation

In SV 1800-2009 concatenations could be used as source expressions for unpacked arrays (section 10.10). I have a query regarding usage of `1 in unpacked array concatenation. If the RTL has something like below

logic [3:0] A [0:0];
initial
begin
               A = {'1};
end

Does this mean that the value of A[0] after assignment will be "1111" or will it be "0001"?

Thanks & Regards
Rohit Goel

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