As you have pointed out in the past, the rules in 23.10 were carried over from the Verilog LRM and were not much updated for SystemVerilog. In Verilog, the data types a parameter could have were very limited. Shalom From: Steven Sharp [mailto:sharp@cadence.com] Sent: Thursday, March 20, 2014 00:07 To: Datta, Kausik; Vreugdenhil, Gordon; Bresticker, Shalom; sv-bc@eda.org Subject: RE: [sv-bc] RE: Value propagation in Parameter with Type The statement about conversion is a shortened and inexact description of what actually happens, which follows the full rules for assignments that have been quoted. I suspect the reason for including this abbreviated mention here is to clarify that the behavior when the parameter has an explicit type is different from when it doesn't. But if you want the fully spelled out rules, you will have to look at the assignment rules. --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Mar 20 02:06:17 2014
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