Re: [sv-bc] RE: Value propagation in Parameter with Type

From: Greg Jaxon <Greg.Jaxon@synopsys.com>
Date: Wed Mar 19 2014 - 11:10:28 PDT
Ditto.
The assignment itself is a signed-to-unsigned built-in coercion, but
it happens after the 2 to 8 bit width coercion is accomplished via sign extension.

On 3/19/2014 9:53 AM, Bresticker, Shalom wrote:

11.8.3 says,

 

11.8.3 Steps for evaluating an assignment

The following are the steps for evaluating an assignment:

— Determine the size of the right-hand side by the standard assignment size determination rules (see 11.6).

— If needed, extend the size of the right-hand side, performing sign extension if, and only if, the type of the right-hand side is signed.

 

So you get

 

parameter UTR p2 = 2'sb11 ;

 

In this case, the RHS is signed.

According to 11.8.3, when size-extending the RHS, it does not matter whether or not the LHS is signed or unsigned. If the RHS is signed, as in this case, sign-extension is performed.

So you should get 8'b11111111.

 

Regards,

Shalom

 

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Datta, Kausik
Sent: Wednesday, March 19, 2014 16:46
To: sv-bc@eda.org
Subject: [sv-bc] Value propagation in Parameter with Type

 

Hi,

For the following testcase what should be the value of p2?

 

Will it be 8’b00000011 or 8’b11111111?

 

Thanks

Kausik

 

 

module bot #(parameter type p1 = logic, parameter p1 p2 = 7)

                  (input in1, output integer out1);

assign out1 = p2;

 

endmodule

 

module top(input  in1, output integer out1);

 

typedef union packed {

        byte      a;

        bit [7:0] b;

}UTR;

 

bot #(UTR, 2'sb11) inst(in1, out1);

 

endmodule

 

 


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