RE: [sv-bc] use before declaration

I think that reference to t  is a selection. Looks that (bacause of
identical syntax) tool's have problem with that. BTW "non-hierarchical "
supervene only one time in LRM. Maybe this word should be changed or
Glossary should be updated ,
Radek

  _____  

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Bresticker, Shalom
Sent: Thursday, December 05, 2013 1:42 PM
To: SV_BC List
Subject: [sv-bc] use before declaration



Hi,

 

Why does the following not fail compilation?

 

module test;

 

wire w = t.s ;

 

struct { logic s; } t;

 

endmodule

 

6.21 says, "A variable declaration shall precede any simple reference
(non-hierarchical) to that variable."

 

The reference to t is non-hierarchical, isn't it?

 

Thanks,

Shalom

 

Shalom Bresticker 
Communications & Storage Infrastructure Group Silicon Engineering

Intel Jerusalem, Israel 
+972  2 589 6582 (office) 
+972 54 721 1033 (cell) 
 <http://www.linkedin.com/in/shalombresticker>
http://www.linkedin.com/in/shalombresticker 

 

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