[sv-bc] RE: streaming_concatenation to net

From: Brad Pierce <Brad.Pierce@synopsys.com>
Date: Tue Sep 17 2013 - 08:10:57 PDT
Hi Shalom,

In my opinion this usage is completely legal and the BNF needs to be fixed, because, as in constant_expression, A.8.5 is trying to apply syntactic tools to semantic rules, and here in Mantis 4693<http://www.eda.org/svdb/view.php?id=4693> it's leading to some apparently absurd results. Why would streaming_concatenations on the left-hand side of a continuous assignment (such as in a port connection) become illegal just because the expressions in it are nets instead of variables?

For example, why would the second assignment in the following, supported by current tools, be illegal, just because out2 is a net?

module test( input [3:0] in,

             output logic [3:0] out1,

             output wire [3:0] out2);

  assign {>>{out1}} = in;

  assign {>>{out2}} = in;

endmodule
-- Brad

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Bresticker, Shalom
Sent: Tuesday, September 17, 2013 1:56 AM
To: SV_BC List
Subject: [sv-bc] streaming_concatenation to net

Hi,

According to the BNF, a net may not be the target of a streaming_concatenation:

net_lvalue ::=
  ps_or_hierarchical_net_identifier constant_select
| { net_lvalue { , net_lvalue } }
| [ assignment_pattern_expression_type ] assignment_pattern_net_lvalue

variable_lvalue ::=
  [ implicit_class_handle . | package_scope ] hierarchical_variable_identifier select46
| { variable_lvalue { , variable_lvalue } }
| [ assignment_pattern_expression_type ] assignment_pattern_variable_lvalue
| streaming_concatenation47

So for example,

module top;
wire out2,out1;
assign {>>{out2}} = out1;
endmodule

is not legal, but it is legal if out2 is declared as logic.

Why the difference?

Thanks,
Shalom


Shalom Bresticker
Intel, Networking Division DA, Jerusalem, Israel
+972  2 589 6582 (office)
+972 54 721 1033 (cell)
http://www.linkedin.com/in/shalombresticker




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Received on Tue Sep 17 08:11:14 2013

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