Interface classes are cool because it's a versatile feature. Some of these I've taken from blogs, presentations or papers that I otherwise wouldn't have considered: 1) TLM implementations; E.g. interface classes for blocking_put, nonblocking_get, etc... 2) Callbacks; E.g. a Callback interface class that prototypes an execute task and a Caller interface class that prototypes a register(Callback) function 3) A project can define a common API to use with IPs delivered by different 3rd parties. E.g., A project can extend a USB BFM and a PCI-Express BFM from different 3rd parties to both implement the same interface class so that there is a common API to use with both. 4) A 3rd party can defining a generic API for their BFM model so that a project can define their own class that implements that API. E.g. a USB BFM may accept an object of any class type as long as it implements the USB interface class API. That interface class would prototype functions like get_address, get_data, set_data, etc..., which is how the USB model would interact with the transaction object. 5) Empty interface classes that imply usage considerations E.g. Copyable to indicate that you can safely create a shallow copy; Threadsafe to indicate that it is safe to execute its methods tasks inside a fork etc... External code would attempt to dynamically cast an object before using it in a particular context to make sure that it's safe. 6) Make different classes containable together, even if they have no common base class; E.g. a Registry class that contains a hash of objects that implement the Registered interface class. -Brandon From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Brophy, Dennis Sent: Wednesday, May 29, 2013 11:42 AM To: Alsop, Thomas R; Brad Pierce; Bresticker, Shalom; sv-ac@eda.org; sv-bc@eda.org; sv-cc@eda.org; sv-ec@eda.org; sv-dc@eda.org; IEEE P1800 Working Group (ieee1800@eda.org) Cc: Cliff Cummings Subject: [sv-ec] RE: DAC Presentation of SV-2012 Enhancements - Cliff requests your input Tom, You want to enhance "soft constraints" already??? What needs to be done? -Dennis From: owner-sv-bc@eda.org<mailto:owner-sv-bc@eda.org> [mailto:owner-sv-bc@eda.org] On Behalf Of Alsop, Thomas R Sent: Wednesday, May 29, 2013 11:39 AM To: Brad Pierce; Bresticker, Shalom; sv-ac@eda.org<mailto:sv-ac@eda.org>; sv-bc@eda.org<mailto:sv-bc@eda.org>; sv-cc@eda.org<mailto:sv-cc@eda.org>; sv-ec@eda.org<mailto:sv-ec@eda.org>; sv-dc@eda.org<mailto:sv-dc@eda.org>; IEEE P1800 Working Group (ieee1800@eda.org<mailto:ieee1800@eda.org>) Cc: Cliff Cummings Subject: [sv-bc] RE: DAC Presentation of SV-2012 Enhancements - Cliff requests your input Hi Cliff, I agree with Brad, these are my favorites too. Brandon Tipp might have some recent examples for the interface class. We have talked about using this in UVM but no firm plans yet. The parameterized function enhancement is something Intel wanted as well. We have function libraries that are hand specialized and this allows us to create template versions. I'll see if I can dig up an example of how we are using this and pass it along. I would add 'soft constraints' to this list. Clause 18.5.14. -Tom From: owner-sv-ec@eda.org<mailto:owner-sv-ec@eda.org> [mailto:owner-sv-ec@eda.org] On Behalf Of Brad Pierce Sent: Wednesday, May 29, 2013 11:26 AM To: Bresticker, Shalom; sv-ac@eda.org<mailto:sv-ac@eda.org>; sv-bc@eda.org<mailto:sv-bc@eda.org>; sv-cc@eda.org<mailto:sv-cc@eda.org>; sv-ec@eda.org<mailto:sv-ec@eda.org>; sv-dc@eda.org<mailto:sv-dc@eda.org>; IEEE P1800 Working Group (ieee1800@eda.org<mailto:ieee1800@eda.org>) Cc: Clifford E. Cummings (cliffc@sunburst-design.com<mailto:cliffc@sunburst-design.com>) Subject: [sv-ec] RE: DAC Presentation of SV-2012 Enhancements - Cliff requests your input Hi Cliff, My favorite SV12 enhancement is Java-style interface classes. As Dave implies in his original paper (http://bradpierce.files.wordpress.com/2010/03/multiple_inheritance_sv.pdf), interface classes could be used to simplify the OVM TLM library code as well as the OVM/VMM Interop library. My explanation of interface classes aimed at those who are more familiar with SV modports than Java is http://bradpierce.wordpress.com/2013/02/16/sv12-interface-classes-think-of-them-as-next-gen-modports/ . Parameterized functions are not actually an enhancement of SV12, but they are first mentioned in the LRM in the SV12. They will be important, too. Here's my advice on how to use them http://bradpierce.wordpress.com/2013/04/20/sv12-deliver-parameterized-functions-with-let-expressions/ . -- Brad From: owner-sv-bc@eda.org<mailto:owner-sv-bc@eda.org> [mailto:owner-sv-bc@eda.org] On Behalf Of Bresticker, Shalom Sent: Wednesday, May 29, 2013 10:50 AM To: sv-ac@eda.org<mailto:sv-ac@eda.org>; sv-bc@eda.org<mailto:sv-bc@eda.org>; sv-cc@eda.org<mailto:sv-cc@eda.org>; sv-ec@eda.org<mailto:sv-ec@eda.org>; sv-dc@eda.org<mailto:sv-dc@eda.org>; IEEE P1800 Working Group (ieee1800@eda.org<mailto:ieee1800@eda.org>) Cc: Clifford E. Cummings (cliffc@sunburst-design.com<mailto:cliffc@sunburst-design.com>) Subject: [sv-bc] FW: DAC Presentation of SV-2012 Enhancements - Cliff requests your input Hi, Cliff Cummings asked me to forward this. Shalom From: Clifford E. Cummings [mailto:cliffc@sunburst-design.com] Sent: Wednesday, May 29, 2013 20:46 To: Bresticker, Shalom Subject: DAC Presentation of SV-2012 Enhancements - Cliff requests your input Hi, All - I have been asked to give a short SystemVerilog-2012 update presentation at DAC. Stu Sutherland has already done a nice update last year at DAC but I would like to take a slightly different approach while sill acknowledging and referencing his DAC presentation. I would like to gather input from as many SystemVerilog-2012 committee members as a I can regarding your favorite SystemVerilog-2012 enhancements. I would suggest that you email me with your five favorite enhancements (feel free to send fewer or more than five favorites). Everyone that sends me a small list of favorites will be acknowledged and thanked in my presentation, which will eventually go into the public domain and will also be posted on my web page. Time is short! All I need is a list of your favorite enhancements, preferably by the end of day on Friday, but you get extra credit for the following: (1) Why each enhancement is on your favorites list. (2) Any examples that show why the enhancement is cool! (3) Reference to specific section numbers of the IEEE 1800-2012 LRM. This is your chance to highlight enhancements that you as a committee member felt was important to the Design and Verification community. Thanks in advance for you short (or extended) feedback. If anybody has a complete list of the enhancements that was compiled separate from Stu's list, you get double-extra credit! Regards - Cliff -- Cliff Cummings - Sunburst Design, Inc. 1639 E. 1320 S., Provo, UT 84606 - 801-960-1996- cliffc@sunburst-design.com<mailto:cliffc@sunburst-design.com> / www.sunburst-design.com<http://www.sunburst-design.com> World Class Verilog, SystemVerilog & OVM/UVM Training --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. 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