Subject: [sv-bc] Non-member submission from [Andy Tsay
Forwarded for Andy Tsay.
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>From SV 3.1 LRM, section 2.3:
Can someone help to clarify if the following
1) wire [3:0] a = '1; // a = 4'b1111 -- all 4 bits set to 1'b1
Thanks,
This archive was generated by hypermail 2b28
: Tue Oct 21 2003 - 21:13:28 PDT
From: Vassilios.Gerousis@Infineon.Com
Date: Tue Oct 21 2003 - 21:11:08 PDT
Hi,
SystemVerilog adds the ability to specify unsized literal single bit values
with a preceding apostrophe ( ' ), but without the base specifier. All bits
of the unsized value are set to the value of the specified bit. In a
self-determined context these literals have a width of 1 bit, and the value
is treated as unsigned.
examples are interpreted correctly?
2) wire [3:0] b = a + '1; // b =(a + 4'b1111) -- all 4 bits set to 1'b1
3) wire [3:0] c = {`1,`1,`1}; // c = 4'b0111 -- self-determined '1 is 1'b1
4) if (a == '1) // if (a == 4'b1111)
5) wire [3:0] d = (a[3] == '1)?b:c; // (a[3] == 1'b1)?b:c
6) bit [3:0] val;
case ('1)
a[3:0]: val = 4'b1111; // if (a[3:0] == 4'b1111) val = 4'b1111;
a[3:1]: val = 4'b1110; // else if (a[3:1] == 3'b111) val = 4'b1110;
a[3:2]: val = 4'b1100; // else if (a[3:2] == 2'b11) val = 4'b1100;
a[3:3]: val = 4'b1000; // else if (a[3:3] == 1'b1) val = 4'b1000;
default val = 4'b0000; // else val = 4'b0000;
endcase
Andy Tsay