Re: [sv-bc] RE: Evaluating bounds in array declarations

Thanks, Steven. So to be backward compatible with Verilog-XL, it looks
like option 3 is the way to go, namely, self-determined evaluation,
but the result treated as a signed integer.

-- Brad

On Mon, Jun 27, 2011 at 7:35 PM, Steven Sharp <sharp@cadence.com> wrote:
> As you say, the issue far predates SV.  Originally it would have come from
> Verilog-XL.  Here are the answers to your examples based on XL.
>
>
>
> Wire w1 has 2 bits, and wire w2 has 1 bit.
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> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Brad
> Pierce
> Sent: Monday, June 27, 2011 3:41 PM
>
> To: sv-bc
> Subject: [sv-bc] Evaluating bounds in array declarations
>
>
>
> In an array declaration, such as
>
>
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>          wire [constant_expression : 0] w;
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> is the constant_expression
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>      1) statically cast to ‘integer’ in the SV style (that is, evaluated in
> the context of an assignment to the signed type ‘integer’), or
>
>      2) evaluated in a self-determined context and used as is (possibly
> unsigned), or
>
>      3) evaluated in a self-determined context, but then cast to an integer?
>
>
>
> I’m guessing 3, but don’t find an answer in the LRM. Why 3? Because the
> issue far predates SV and its static cast, and the result of self-determined
> context used as-is leads to strange results.
>
>
>
> For example, does the following have 2 bits, or a huge number of bits?
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>        wire [ 32’b0 - 1 : 0] w1;  // type(32’b0 – 1) is unsigned
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> For example, does the following have 7 bits or 1 bit?
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>        wire [ 1’b1 + 1’b1 + 1’b1 << 1 : 0] w2;   // 6 == (1’b1 + 1’b1 + 1’b1
> << 1)
>
>
>
> -- Brad
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