[sv-bc] RE: Email Vote: Respond by 8AM PDT Wed Apr 20

From: Steven Sharp <sharp@cadence.com>
Date: Wed Apr 20 2011 - 11:12:37 PDT

I don't have a problem with 1-bit signed variables that can only take on values of 0 and -1 (though that does seem to confuse some people). But a simple 1-bit scalar is not such a variable; it is unsigned by default. So the LRM should specify that.

One problem with the existing text is that it was written for Verilog, before there was a formal concept of a packed array, or an explicit name for the built-in 4-state logic bit. So the description of "reg" seems to be primarily intended for declarations of vector regs, which would now be described as a packed array of logic, because that is how a reg was most often declared. It wasn't really intended to describe the single scalar logic bit that these packed arrays are built from.

________________________________________
From: owner-sv-bc@eda.org [owner-sv-bc@eda.org] On Behalf Of Rich, Dave [Dave_Rich@mentor.com]
Sent: Wednesday, April 20, 2011 1:53 AM
To: Maidment, Matthew R; SV-BC
Subject: [sv-bc] RE: Email Vote: Respond by 8AM PDT Wed Apr 20

I am in favor of all except 2982

$urandom should now be used instead of $random, and any proposal that touches existing cases of this should have this changed.
Also, the example in 25.7.2 should be made legal by the following:

module cpuMod(interface b);
enum {read, write} instr ;
logic [7:0] raddr = $urandom();

For 3384, I agree the wording should use 'packed arrays'. I also agree that you do need to say that a 1-bit scalar is unsigned. Otherwise you could wind up with a variable that can only take on the values 0 and -1 by default.

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Maidment, Matthew R
Sent: Wednesday, April 13, 2011 1:02 AM
To: SV-BC
Subject: [sv-bc] Email Vote: Respond by 8AM PDT Wed Apr 20

-You have until 8am PDT, Wednesday April 20, 2011 to respond -An issue passes if there are zero NO votes and half of the eligible voters respond with a YES vote.
-If you vote NO on any issue, your vote must be accompanied by a reason.
 The issue will then be up for discussion during a future conference call.
-Note: The proposed action is captured in the bug note
       (resolve as duplicate, already addressed, etc.).

As of the April 11, 2011 meeting, the eligible voters are:

Steven Sharp
Francoise Martinolle
Tom Alsop
Shalom Bresticker
Dave Rich
Gordon Vreugdenhil
Alex Gran
Arnab Saha
Eric Coffin
Brad Pierce
Mark Hartoog

SVDB 2595 ___Yes ___No
http://www.eda.org/svdb/view.php?id=2595

SVDB 2976 ___Yes ___No
http://www.eda.org/svdb/view.php?id=2976

SVDB 2977 ___Yes ___No
http://www.eda.org/svdb/view.php?id=2977

SVDB 2982 ___Yes ___No
http://www.eda.org/svdb/view.php?id=2982

SVDB 3026 ___Yes ___No
http://www.eda.org/svdb/view.php?id=3026

SVDB 3062 ___Yes ___No
http://www.eda.org/svdb/view.php?id=3062

SVDB 3274 ___Yes ___No
http://www.eda.org/svdb/view.php?id=3274

SVDB 3362 ___Yes ___No
http://www.eda.org/svdb/view.php?id=3362

SVDB 3384 ___Yes ___No
http://www.eda.org/svdb/view.php?id=3384

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Received on Wed Apr 20 11:12:59 2011

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