[sv-bc] The type() operator should only accept primaries, not general expressions

6.23 introduces the type() operator with the following examples

   var type(a+b) c, d;
   c = type(i+3)'(v[15:0]);

And A.2.2.1 defines

   type_reference ::=
        type ( expression )
      | type ( data_type )

But I think there's no practical need to allow general expressions
here instead of restricting to parenless primaries. For integral types
the restriction could be easily worked around with {}, $unsigned or
$signed to get the same effect

   var type({a+b}) c, d;
   c = type($signed(i+3))'(v[15:0]);

and being forced to do so might remind users that something "funny"
could be going on.

An oddity of the Verilog type system for integral types (6.11.1) is
that the value of an expression, unless it is a parenless primary,
depends on its evaluation context.

For example,

   `define E = (1'b1 + 1'b1 >> 1)

   localparam         P = `E;   // 1'b0
   localparam [1:0] Q = `E;   // 2'b01
   localparam type(`E) R = `E; // 1'b0

   localparam A = (P[0] != Q[0])   // TRUE
   localparam B = (P[0] == R[0])   // TRUE

   function f(logic [0:0] P, logic [1:0] Q);
      return P[0] == Q[0];
   end

   parameter C = f(`E,`E);      // FALSE
   parameter D = f(`E,{`E});    // TRUE
   parameter E = f(`E,$signed(`E)); // TRUE

I think we should change the BNF to

   type_reference ::=
        type ( primary )
      | type ( data_type )

and change its footnote 17 from

  "An expression that is used as the argument in a type_reference
shall not contain any hierarchical references or references to
elements of dynamic objects."

to something like

 "A primary that is used as the argument in a type_reference shall not
be wrapped in paretheses and shall not contain any hierarchical
references or references to elements of dynamic objects."

The example would also need to be modified, but it would be OK to let
the paragraph after it continue to talk about "expression".

-- Brad

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