[sv-bc] Hierarchical references in #(...) instantiations and $bits() constant function calls (1224 and 2856)

According to the comments on http://www.eda.org/svdb/view.php?id=1224 , hierarchical references are allowed in the parameter value assignments in module instantiations, hence the use of param_expression instead of constant_param_expression in A.4.1.1 .

In http://www.eda.org/svdb/view.php?id=2856 , Françoise gives an example of the dangers of allowing hierarchical references in $bits() constant function calls. I think the following is equivalent

  module top;
    child #($bits(inst.v)-1) inst();
  endmodule

  module child #(P = 32);
    bit v[P];
  endmodule

or simply

  module top;
    child #(inst.P-1) inst();
  endmodule

  module child #(P = 32);
    bit v[P];
  endmodule

If hierarchical references are legal within the #(), yet the final example is illegal, then maybe whichever rule makes it illegal could be applied to the $bits() call in Françoise's example.

-- Brad

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