[sv-bc] Query regarding the usage of implicit generate block name in hierarchical reference

Hi,

I have query regarding the usage of implicit generate block (created for unnamed block) in hierarchical references. The LRM, says,

"Although an unnamed generate block has no name that can be used in a hierarchical name, it needs to have a name by which external interfaces can refer to it."

My queries are:

1) Can we use implicit names in hierarchical references.

2) What does "external interfaces" mean? Is it like representing complete hierarchy and things like that

Example:

module test (input [7:0] in, input clk, output [7:0] out1);
 genvar i;
 generate
 for(i=0; i < 8; i = i+1)
 begin
                flop my_flop(in[i], clk, out1[i]);
                defparam genblk1[i].my_flop.P1 = i; // Is this usage of implicit names (genblk1) valid
 end
 endgenerate
endmodule

Thanks & Regards,
Harpreet Singh

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