RE: [sv-bc] Generate with multiple begins

Hi,

Regarding #1, they were allowed in Verilog-2001 and then disallowed in Verilog-2005 and SystemVerilog.

Shalom

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Gal Vardi
Sent: Thursday, February 24, 2011 10:09 AM
To: SV-BC
Subject: RE: [sv-bc] Generate with multiple begins

Hi,

We just ran into this limitation with one of the synthesis tools.

In the plain Verilog-2001 code we currently use, there are begin-end at the toplevel, and "bare" begin-ends inside generate. No tool complained until Jan 2011 (and we usually check a wide range of them from different vendors)

1. Can I understand exactly which standard allows each of "toplevels" and "bares", and which standard forbids. It is not straightforward from the text in the standards.

2. If it is not too late to argue, I'd like to humbly add my personal opinion:

            Both the begin-end at the toplevel and the bare ones inside are useful:

Toplevels: if you have couple of if/case/for statements within a single generate block

Bares: within a hierarchical if/then/else or hierarchical case statements.

I also like the orthogonally raised by Paul Graham. Orthogonally for a designer means simplicity: You can place a [named] begin-end wherever you like, it will never be an error.

A related issue is the naming convention of the un-named begin-end blocks, and how to keep hierarchical naming consistency between different tools, from Equivalence to SDC format.

I prepared a suggestion regarding that issue and can post it if there is a related thread in this workgroup or else where you may suggest.

Regards,

Gal Vardi

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