Re: [sv-bc] Bit/Part select of modport named argument

So we could legally write i.j[0][0][0][0][0][0] and it would yield the
same as i.j?

-- Brad

On Fri, Feb 4, 2011 at 9:24 PM, Steven Sharp <sharp@cadence.com> wrote:
> How can you distinguish a scalar from a 1-bit vector in this situation?  I think the distinction disappears when used in an expression, and the self-determined type is the same.
>
>
> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Brad Pierce
> Sent: Friday, February 04, 2011 11:18 AM
> To: Surya Pratik Saha
> Cc: sv-bc@eda.org
> Subject: Re: [sv-bc] Bit/Part select of modport named argument
>
> "The self-determined type of the port expression becomes the type for the port." Shouldn't you be able to use the name of the port in any way that's consistent with its type? In this case, it has a scalar type, and it doesn't make sense to be indexing into a scalar type.
>
> -- Brad
>
> On Fri, Feb 4, 2011 at 2:15 AM, Surya Pratik Saha <spsaha@cal.interrasystems.com> wrote:
>> Hi,
>> I have a design like:
>> interface iface;
>>    logic [2:0] x;
>>    modport mport (input .j (x[1]));
>> endinterface
>>
>> module top;
>> iface i ();
>> foo f (i.mport);
>> endmodule
>>
>> module foo (iface.mport i);
>>    initial begin
>>        i.j[1] = 1; // Bit select of modport named argument
>>    end
>> endmodule
>>
>> Is bit/part select of modport named argument allowed? I am also not
>> sure what is the meaning of that if it is allowed. Though some
>> standard tools do not give any meaningful error.
>>
>> --
>> Regards
>> Surya
>>
>>
>>
>>
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