Subject: Re: [sv-bc] Proposals for SV3.1a
From: Michael McNamara (mac@verisity.com)
Date: Tue Sep 23 2003 - 11:06:16 PDT
yes, the following is illegal,
wire w = a ? and(b, c) : or(d, xor(e, f));
of course, one could write:
wire w = a ? b&c : d|e^f;
which is shorter, and works since the epoch...
-- On Sep 23 2003 at 10:13, Dave Rich sent a message:
> To: krolnik@lsil.com, sv-bc@eda.org
> Subject: "Re: [sv-bc] Proposals for SV3.1a"
> Adam,
>
> You cannot write that statement today because (and, or, xor) are Verilog
> keywords for gate-level primitives. See section 7.2 of Verilog 1364-2001
> for the current definition of syntax for gate-level primitives.
>
> You're not the only one who thought this syntax was already legal, which
> is why this enhancement makes a lot of sense.
>
> Dave
>
>
> Adam Krolnik wrote:
>
> >
> >
> > HI Dave;
> >
> >
> > A question about the function proposal.
> >
> > I do not understand the benefits your proposal provides.
> >
> > E.g. I can write this statement today - what is the difference
> > between what I can do today and what your proposal provides?
> > Maybe having the definitions of and(), or(), xor() would help...
> >
> > wire w = a ? and(b, c) : or(d, xor(e, f));
> >
> >
> > THanks
> >
> >
> > Adam Krolnik
> > Verification Mgr.
> > LSI Logic Corp.
> > Plano TX. 75074
> >
> >
> >
>
> --
> --
> David.Rich@Synopsys.com
> Technical Marketing Consultant
> http://www.SystemVerilog.org
> tele: 650-584-4026
> cell: 510-589-2625
>
>
This archive was generated by hypermail 2b28 : Tue Sep 23 2003 - 11:10:13 PDT