Re: [sv-bc] logic -vs- ulogic

Subject: Re: [sv-bc] logic -vs- ulogic
From: Jim Lewis (Jim@SynthWorks.com)
Date: Thu Sep 18 2003 - 13:04:00 PDT

I personally would prefer SV uses logic and bit.

I think the shorter name in VHDL was ment to indicate
the preferred type.

My opinion is that the preferred type for both languages
should be the unresolved type. This is because 99% of
all connections in a chip are point to point and not
tristate busses.

If you are going to introduce a resolved type, it should
have the longer name such as rlogic and rbit to indicate
that it is not expected to be the preferred type.

Cheers,
Jim Lewis 

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Karen Pieper wrote:

> Here is some mail that bounced from Mike Treseler:
> 
> 
>> >From owner-sv-bc Tue Sep 16 15:04:57 2003
>> Received: from vir2.relay.fluke.com (vir2.relay.fluke.com 
>> [129.196.184.26])
>>         by server.eda.org (8.12.0.Beta7/8.12.0.Beta7) with ESMTP id 
>> h8GM4s6O007632
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>> Received: from fluke.com ([129.196.180.170] RDNS failed) by 
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>>         Tue, 16 Sep 2003 15:04:50 -0700
>> Message-ID: <3F678902.4040104@fluke.com>
>> Date: Tue, 16 Sep 2003 15:04:50 -0700
>> From: Mike Treseler <tres@fluke.com>
>> Organization: Fluke Networks
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>> Subject: logic -vs- ulogic
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>> X-OriginalArrivalTime: 16 Sep 2003 22:04:50.0977 (UTC) 
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>> TO: The SystemVerilog Design Committee
>>
>>
>>
>> The SystemVerilog types: "logic"  and  "bit."
>> ought to be renamed     "ulogic"  and "ubit."
>>
>> to both clarify that these are unresolved types,
>> and to better match the related VHDL type std_ulogic.
>>
>>
>>
>>
>>   -- Mike Treseler
>>      Fluke Networks
> 
> 
> 
> 
>

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