[sv-bc] RE: Cooperation request in definition of simulation semantics of emerging checker constructs

I will add a brief review of these issues to the agenda for the next SV-BC meeting and assess how SV-BC involvement in AC matters will impact to the WG's approved SV-BC goals.

Matt

From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Korchemny, Dmitry
Sent: Tuesday, November 16, 2010 1:25 AM
To: sv-bc@eda.org
Cc: sv-ac@eda.org; neil.korpusik@oracle.com; Karen Pieper
Subject: [sv-ac] Cooperation request in definition of simulation semantics of emerging checker constructs

Hi SV-BC,

SV-AC is starting working on the following checker enhancements:

* 2093: Checker construct (Mantis 1900) should permit output arguments

* 3034: Allow continuous and blocking assignments in checkers

* 3033: Allow procedural control statements in checkers

* 2743: Allow subroutine_call_statement in a checker

* 2751: P1800-2009: checker formal arguments may not be connected to interfaces // WHY

These enhancements have been approved by the Working Group and are targeted for the current PAR. The implementation of these enhancements is related to definition of a consistent simulation semantics for the new constructs and may have an implication on the rest of the language. SV-AC requests your help and cooperation in reviewing and discussing relevant parts of the emerging proposals to keep SystemVerilog language consistent and to reduce the changes to the absolute necessary minimum.

Thanks,
Dmitry
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