Re: [sv-bc] Re: [sv-ac] Identifier usage before declaration in assertion

Hello Ben,

According to LRM section 16.3
"The immediate assertion statement is a test of an expression performed
when the statement is executed in the
procedural code. The expression is nontemporal and is interpreted the
same way as an expression in the
condition of a procedural if statement."

So for following testcase

module top(input clk, input [3:0] iT, output [3:0] oT);
initial
begin
    assert (aa == 4'b0000)
        $display("true");
        else
            $display("false");
   
   if(aa == 4'b0000)
        $display("true");
    else
       $display("false");

end
reg [3:0] aa;
endmodule // top

Immediate assertion statement and if statement are equivalent. Standard
tools are failing for if while passing for
immediate assertion statement which should not be the case.

So it's not sure that what should be checked at analysis and what should
be checked at elaboration.

Regards,
dhiRAj

ben cohen wrote:
> LRM 3.12 Compilation and elaboration addresses the elaboration.
> Elaboration takes care of the variables being declared in the design.
> LRM: "Not all syntax and semantics can be checked during
> the compilation process."
> Ben Cohen
>
> On Sun, Jul 11, 2010 at 11:21 PM, Surya Pratik Saha
> <spsaha@cal.interrasystems.com <mailto:spsaha@cal.interrasystems.com>>
> wrote:
>
> Hi,
> For the following case:
> module top(input clk, input [3:0] iT, output [3:0] oT);
> assert property (@(posedge clk) (aa == 4'b0000)) ;
> reg [3:0] aa;
> always @(posedge clk)
> aa <= iT;
> assign oT = aa;
> endmodule // top
>
> All the standard simulators pass the case. Please note that 'aa'
> is used before it is declaration in the assertion statement. I
> could not find any text in the LRM regarding this. What is the
> reason of this?
>
> --
> Regards
> Surya
>
>
>
>
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