Re: [sv-bc] RE: [sv-ec] Are variable-width part selects already part of the SV language? (Mantis 2684)

Shalom,

In verilog any constant part-select or variable part-select is synthesizable. In each case the width of the part-select is a constant at synthesis time.

In vhdl, the possibilities are greater. Ignoring the special case of "constant" variables, you can have part-selects like:

    A[x to x+7];
    A[8*x to 8*x+7]
    A[8*x to 8*(x+1)-1]

Each one could be supported, but they get trickier to analyze. How about:

    y := 2*x+1;
    A[8*x to 4*y-1];

Then special cases like:

    A <= (others => '0');
    A(x downto 0) <= (others => '1'); -- i.e., A = (1<<x)-1

or:

    A <= B(msb downto x) & C(x-1 downto lsb)

Syntactically these are all the same. There's a lot of ad-hoc logic needed to see which cases can be handled, or are worth handling.

My suggestion, from a synthesis point of view, is to see which coding styles require variable-width part-selects, and devise a syntax which makes clear to the synthesis tool that this is a supportable construct. A too-general syntax like vhdl has just makes it harder to support.

Paul

----- Original Message -----
From: "Shalom Bresticker" <shalom.bresticker@intel.com>
To: "Paul Graham" <pgraham@oasys-ds.com>
Cc: sv-bc@eda.org, "SV_EC List" <sv-ec@eda.org>, "brad pierce" <brad_pierce@acm.org>, "Dave Rich" <Dave_Rich@mentor.com>
Sent: Friday, May 7, 2010 9:51:50 AM
Subject: RE: [sv-bc] RE: [sv-ec] Are variable-width part selects already part of the SV language? (Mantis 2684)

Yes, I looked at this.

That may be one of the reasons that VHDL simulation was stated in the past to be slower than Verilog. I don't know whether that is still true.

I also looked at what VHDL part-selects are considered synthesizable. The main differences are that (1) variables that are assigned constant values are allowed, and (2) loop index variables (called "parameters" in VHDL) are allowed. Loop unrolling allows the synthesis tool to treat them as constants.

Regards,
Shalom

> -----Original Message-----
> From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On
> Behalf Of Paul Graham
> Sent: Friday, May 07, 2010 4:44 PM
> To: Bresticker, Shalom
> Cc: sv-bc@eda.org; SV_EC List; brad pierce; Dave Rich
> Subject: Re: [sv-bc] RE: [sv-ec] Are variable-width part
> selects already part of the SV language? (Mantis 2684)
>
> For what it's worth, variable width and variable offset part
> selects have always been part of vhdl. Vhdl has no special
> syntax to distinguish variable part selects from constant
> part selects, so a tool has to do some analysis to see which
> forms it can support and which it can't.
>
> Paul
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