[sv-bc] Fwd: Cliff's SV-BC Enhancements for 2012

Slides Link:
http://www.eda.org/sv-ieee1800/Meetings/2010/February/Presentations/Cliff%20Cummings%20Presentation.pdf

>Date: Sun, 11 Apr 2010 22:55:05 -0700
>To: sv-bc@eda.org
>From: "Clifford E. Cummings" <cliffc@sunburst-design.com>
>Subject: Cliff's SV-BC Enhancements for 2012
>
>Hi, Matt -
>
>Apologies for not getting this out sooner. I have to fly to Europe
>on Monday and have asked Tracy McDermott from my office to sit in as
>my proxy at the next two SV-BC conference calls and take notes in
>case I have been asked to provide info to the committee. Tracy has
>my vote or abstain authority.
>
>Cliff's SV-BC Top Feature Requests (referencing my slides from the
>DVCon meeting):
>
>(1) X-Optimism/X-Pessimism resolution (slides 5-13)
>(2) Connectivity checking (slides 14-19)
>(3) Signed Operators (slides 20-23)
>(4) Allow procedural assignments to net types (slides 24-28)
>(5) `default_nettype logic (slides 29-30)
>(6) Reproducible randomization of initial states (slide 32 -
>Cummings-Bening SNUG paper)
>(7) Always-assign race-removal (slide 33)
>(8) Regular expressions using .* (Slide 34 - like Verilog EMACS mode)
>(9) Remove 1-bit wire declaration requirement for .* (Slide 24)
>(10) ANSI style ports and parameters - allow either comma or
>semicolon separators (slide 36)
>(11) Treat Verilog-2001 attributes like strings (slide 37)
>(12) Fix UDP event scheduling for reg-UDPs (slide 37)
>(13) Intentional bit-reversal usage (slide 37)
>(14) NBA delay macro <=# (no slide but almost equivalent to <= #1
>(can be turned off))
>
>Regards - Cliff

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14355 SW Allen Blvd., Suite #100, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
World Class Verilog & SystemVerilog Training

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