[sv-bc] RE: Top-25 SV-BC requests

Hi,

The following are Intel enhancement issues listed by Matt.

 696: Parameterized tasks, functions and data types
 210: Generate for module port definitions and instance port connections
2684: Variable part-selects
1566: Variable number of task and function arguments

Macro improvements
1084: Logical expressions: http://www.eda.org/svdb/view.php?id=1084
1697: looping: http://www.eda.org/svdb/view.php?id=1697
 
Improved Checking
2680/1144: Warning on out-of-bounds array writes

I add the following as part of Improved Checking:
1067: out-of-range or x/z index to array of reals (the item talks about much more than just reals)

I will add the following as an Intel enhancement issue:
3025: Introduce elaboration-time function for type compatibility check

I will express support for the following:

Interface issues:
2114: Problems in definition of modports
1861: Suggestion for major enhancement of modports
 905: No way to use type from interface in ANSI-style port declaration

2273: Port declaration issues
2593: Omitting types in port declaration

  99: 2-state wildcard for case-items (in case, casez, and casex)
 104: VCD dumping for all types
1350: $ and $isunbounded issues
1156: vector version of ?: operator
2832: empty concatenations and zero-width part-selects

Macros:
1333: text macro actual argument syntax too restrictive
1339: clarify whether leading/trailing white space should be removed from macro text
1537: macros: `` within escaped identifiers
1563: allow macro argument passing by name, like task/funcs
1202: define standard preprocessor

I wish I could have listed more, but I stopped at 25...

Shalom
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