Re: [sv-bc] expressions not allowed in RHS or continous assign or on port connection list

>Date: Fri, 09 Apr 2010 11:37:41 -0700
>From: John Michael Williams <john@svtii.com>

>I think what you mean is that there is no guarantee of the
>sequence of execution of a continuous assignment relative
>to other concurrent blocks (such as always or initial).

This is not just an issue of ordering relative to other
concurrent blocks in time slices when a continuous assignment
evaluates. Whether a continuous assignment will evaluate at
all in a given time slice is not well-defined. If there is
a change in one of its operands that would change the value
of the expression, then it must evaluate. But it might or
might not evaluate in some other situations. If it evaluates
extra times but keeps getting the same result, this doesn't
matter as long as there are no side effects of the evaluation.

For example, consider the assignment

        assign out = vector[3];
        
Should this be evaluated only when bit 3 of vector changes?
Or can it evaluate whenever vector changes, with the selection
of bit 3 being part of the evaluation? The LRM doesn't really
specify this, nor should it. Implementations need to be free to
do this however they choose. In practice, this may depend on
whether vector is a variable or a net, and whether the net is
vectored or scalared. And as long as there are no side effects,
the difference is invisible.

Any side effect that exposes exactly when or how often a
continuous assignment expression is evaluated is not going to
behave in a predictable or portable way.

Steven Sharp
sharp@cadence.com

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