RE: [sv-bc] expressions not allowed in RHS or continous assign or on port connection list

There has been in recent years a tendency to try to make illegal various construct uses on the grounds that the user *might* write something that causes problems instead of "trusting the user to write a reasonable function" and warning him to avoid certain uses that would cause problems, thereby outlawing certain useful forms.

SV and Verilog have come under criticism both for being too lenient (by those who like strict type-checking, etc.) and for being too strict. Both camps often bring VHDL as a counter-example. I personally favor the lenient school, relying on coding guidelines to guide users and on code checkers to detect bad uses.

Shalom

> Yes, it is possible for a user to call a function in a
> continuous assignment
> which has a side effect. This could cause a problem.
> However, it is also
> possible that the user has correctly written a pure function
> that does not
> have any side effects. Rather than specifying extra rules
> about what kind
> of functions are legal here, the LRM may be trusting the user
> to write a
> reasonable function. And function calls are too useful to be outlawed
> completely here. Making certain functions illegal here would
> also not be
> backward compatible with Verilog.
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