RE: [sv-bc] Is '1 allowed in a concatenation?

From: Clifford E. Cummings <cliffc@sunburst-design.com>
Date: Mon Mar 22 2010 - 10:24:08 PDT

Hi, Shalom -

It is a bit of a stretch, but here is why I think we are covered
(this could be better):

At 05:46 AM 3/22/2010, Bresticker, Shalom wrote:
>Is a literal like '1 allowed in a concatenation?
>
>On the one hand, 11.4.12 says, "Unsized constant numbers shall not
>be allowed in concatenations. This is because the size of each operand in
>the concatenation is needed to calculate the complete size of the
>concatenation."
>
>On the other hand, 5.7.1 says, "An unsized single-bit value can be
>specified by preceding the single-bit value with an apostrophe ( '
>), but without the base specifier. All bits of the unsized value
>shall be set to the value of the specified bit. In a self-determined
>context, an unsized single-bit value shall have a width of 1 bit,
>and the value shall be treated as unsigned."

(1) unsized single-bit value can be preceded with an apostrophe ( ' )
(2) All bits of the unsized value shall be set to the value of the
specified bit
(3) In a self-determined context, an unsized single-bit value shall
have a width of 1 bit (now it has a size)

Just my reading of a somewhat obscure passage. I don't think anyone
would object to better wording, if you can propose it.

Regards - Cliff

At 07:47 AM 3/22/2010, Bresticker, Shalom wrote:
>Hi, Cliff.
>
>It is clear that if '1 is legal in a concatenation, then it is a single bit.
>The question is whether it is legal.
>
>At best, the LRM is ambiguous about it.
>
>Since 11.4.12 says that unsized constants are not allowed in
>concatenations and 5.7.1 calls '1 unsized, it is reasonable to
>conclude that it is not legal. As pointed out, a simple unsized
>constant is also not allowed even though its size is well-defined (32 bits).
>
>Regards,
>Shalom
>
> > -----Original Message-----
> > From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On
> > Behalf Of Clifford E. Cummings
> > Sent: Monday, March 22, 2010 4:40 PM
> > To: sv-bc@eda.org
> > Subject: Re: [sv-bc] Is '1 allowed in a concatenation?
> >
> > Hi, Shalom -
> >
> > There may be a wording problem in the standard, but adding '1 or '0
> > to a concatenation is the same as adding 1'b1 or 1'b0.
> >
> > I point this out as an exception to '0 and '1 expansion in my
> > training classes.
> >
> > Rationale:
> > What would be expected if you had declared:
> > logic [15:0] data1 = {'1,8'hAA};
> > logic [15:0] data2 = {8'hAA, '1};
> > logic [15:0] data3 = {'0, 8'hAA,'0, '1};
> >
> > There would have to be some rather interesting assumptions on the
> > part of the compiler to determine the intended size of the '0 or '1
> > expansion, including a number of special cases. The assumptions might
> > not be obvious to an end user and debugging these declarations might
> > be rather time-consuming.
> >
> > It was just easier to say that in these self-determined contexts,
> > each '1 or '0 is just a single bit.
> >
> > Regards - Cliff

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14355 SW Allen Blvd., Suite #100, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
World Class Verilog & SystemVerilog Training

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Received on Mon Mar 22 10:24:31 2010

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