Subject: RE: [sv-ec] RE: [sv-bc] Question on memory pattern file formats in SV
From: Shalom.Bresticker@motorola.com
Date: Fri Aug 22 2003 - 00:33:47 PDT
I would assume that any enhancement to $readmem would apply to $fread as well.
I dislike the situation that memories (1-dimensional arrays of vectors or
scalars) get a special status in Verilog. That is, there are things you can
do with memories which you can not do in n-dimensional arrays. One way to
reduce that difference would be to treat an array
slice of the last dimension as a memory.
That is, if I declare an array A[5:0][4:0][6:0], then I could treat
A[5][3] as a memory of dimension [6:0].
Shalom
> Note that with a Verilog loop version, any of these variations can be
> written with minor changes to the code. Should $readmem provide the
> same level of flexibility, or give up and only provide a limited subset
> of the possibilities for multi-dimensional arrays?
-- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
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