[sv-bc] RE: [sv-cc] Notes from 26 February 2010 SystemVerilog Requirements Gathering Meeting

From: Bresticker, Shalom <shalom.bresticker@intel.com>
Date: Tue Mar 02 2010 - 02:50:27 PST

Also, just for the record, in the Combined Ordinal column, the "Assertions & Checkers" category is in a tie for #3 with "Connections to Analog", but they appear as #4 and #3 respectively.

I had wondered how we would sort and rank all the ideas that were presented. The way that was chosen is quite reasonable, although of course the Working Group is not obligated to accept it.

Regards,
Shalom

________________________________
From: Bresticker, Shalom
Sent: Tuesday, March 02, 2010 11:48 AM
To: 'Rich, Dave'
Cc: IEEE 1800; sv-bc@eda.org; sv-ec@server.eda.org; sv-cc@eda.org; sv-ac@eda.org
Subject: RE: [sv-cc] Notes from 26 February 2010 SystemVerilog Requirements Gathering Meeting

Thanks.

According to my count, the Users have a total of 152 points and the Producers have 153 points, that is, an equal representation for each group.

Shalom

________________________________
From: Rich, Dave [mailto:Dave_Rich@mentor.com]
Sent: Tuesday, March 02, 2010 6:25 AM
To: Bresticker, Shalom
Cc: IEEE 1800; sv-bc@eda.org; sv-ec@server.eda.org; sv-cc@eda.org; sv-ac@eda.org
Subject: RE: [sv-cc] Notes from 26 February 2010 SystemVerilog Requirements Gathering Meeting

Shalom,

The link is

http://www.eda.org/sv-ieee1800/Meetings/2010/February/Presentations/SV%20Req%20Meeting.xls

Note that the list was created ad-hoc from memory after the last presentation, and not a collection all of the issues or priorities presented.

Dave

From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On Behalf Of Bresticker, Shalom
Sent: Monday, March 01, 2010 7:59 PM
To: Brophy, Dennis; IEEE P1800 Working Group; sv-ac@eda.org; sv-bc@eda.org; sv-cc@eda.org; sv-ec@eda.org
Subject: RE: [sv-cc] Notes from 26 February 2010 SystemVerilog Requirements Gathering Meeting

Hi,

I just looked at this briefly for now.

Some of the affiliations in the attendance list are not correct. Jonathan Bromley represents Verilab, not Doulos. Peter Flake is listed as "Self", but later as "ELDA". A few of the names are listed last name first, can you correct?

The hyperlinks don't work.

For V-AMS, I have attached a document that was presented in the V-AMS committee. Is this what was presented to you?

Thanks,
Shalom

________________________________
From: owner-sv-cc@eda.org [mailto:owner-sv-cc@eda.org] On Behalf Of Brophy, Dennis
Sent: Tuesday, March 02, 2010 4:20 AM
To: IEEE P1800 Working Group; sv-ac@eda.org; sv-bc@eda.org; sv-cc@eda.org; sv-ec@eda.org
Subject: [sv-cc] Notes from 26 February 2010 SystemVerilog Requirements Gathering Meeting
All,

The notes have been posted at http://www.eda.org/sv-ieee1800/Meetings/2010/February/Presentations/26-February-2010-Req-Gather-Mtg-Notes.pdf.

If there is additional information that should be included in the notes, please let me know.

Regards,

Dennis

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Received on Tue Mar 2 02:51:47 2010

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