Subject: [sv-bc] Proposal for : SV-BC Issue 20: Revisit (old) SV-BC19-60 to develop a more complete solution
From: Jacobi, Dan (dan.jacobi@intel.com)
Date: Mon Jul 28 2003 - 01:27:44 PDT
Spec
====
This E-mail deals with the SV-BC issue :
SV-BC Issue 20: Revisit (old) SV-BC19-60 to develop a more complete solution
The Initial Problem
==============
We identified a problem with the generic interface ports which might cause the parsers
to get confused in such test case (currently this test case does not comply to the
System-Verilog 3.1 standard)
1) Interface myint (aGeneric, bGeneric);
2) interface aGeneric;
3) interface bGeneric;
4) endinterface // Does this ‘endinterface’ refer to line 1 or line 2 ?
For more information regarding the problem (Motivation) see
http://www.eda.org/vlog-pp/sv-bc/hm/0542.html
System-Verilog 3.1 Status
===================
We decided that it should be illegal to use generic interface ports using the Verilog 95
list of ports style. The use of generic interface is permitted only by using the
ANSI style list of port declarations such as
1) interface myint (interface aGeneric, interface bGeneric);
2) endinterface // No Dilemma here thee ‘endinterface’ belongs to line 1
In the System-Verilog 3.1 LRM the BNF (annex A) was changed, also proper language
was added to sections 18.5 and 19.2.3.
For more details see
http://www.eda.org/sv-bc/hm/0598.html
Still Problematic
============
The use of Verilog 95 list of ports style is some times needed to declare port
expressions and explicit ports, that can not be declared using the ANSI style list of port
declarations. Such as:
module explicit_ports(.p1(i), .p2(i), p3());
inout i;
…
endmodule
module expression_ports(a[3:0], a[6:4], {b, c} );
input [6:0] a;
input b, c;
…
endmodule
The Bad News
===========
After spending a better part of the day I still could not find a generic solution that will
enable the use of the Verilog 95 non-ANSI style list of ports together with the generic
interface ports, with out adding a new keyword for generic interfaces
(I am strongly against adding new keywords).
Some bas solutions I thought of (However I do not like them)
1. Add a new keyword for generic interfaces such as
Interface myint (aGeneric, bGeneric);
genericinterface aGeneric;
genericinterface bGeneric;
endinterface
2. Disable the use of generic interface ports as interface ports
(They are still O.K. as module ports) The following will be considered illegal
interface myint (aGeneric, bGeneric);
interface aGeneric;
interface bGeneric;
endinterface
But the following will be considered legal
module mymod (aGeneric, bGeneric);
interface aGeneric;
interface bGeneric;
endmodule
3. Disable the declaration of nested interfaces. (nested Modules are still O.K.)
The following will be considered illegal
interface outer (p1, p2);
interface outer (p3, p4);
…
endinterface;
endinterface
As I said I think all of these 3 solutions are not satisfying
Bottom Line
=========
My final proposal is to make ant more changes (keep the status as it in the System-Verilog 3,1 LRM)
However I will be happy to receive more proposals for solving this issue, and to receive
other opinions of the rest of the SV committees’ members
Dan Jacobi
Tel : (972)-4-8655855
INet : 465-5855
This archive was generated by hypermail 2b28 : Mon Jul 28 2003 - 01:30:54 PDT