Subject: Re: [sv-bc] Repeat count 0
From: Greg Jaxon (Greg.Jaxon@synopsys.com)
Date: Wed Jul 16 2003 - 17:26:14 PDT
Verilog/System Verilog has ignored or ruled out "emptiness" of all
sorts - it is either impossible to achieve or completely undefined
once achieved.
One item that system verilog accidentally added to the undefined bin is
empty structures (that have no fields), arrays thereof, and
expressions cast to such types.
Similarly the number'(e) form of casting was probably meant as size'(e),
unless you really want 0'(e) and 1'b0'(e) to be valid syntax.
Much as I miss APL empty arrays, I think Verilog would be safer if
the committees agreed to rule out emptiness altogether. &{} != |{}.
Greg Jaxon
Steven Sharp wrote:
> While the production of a 1-bit zero is the most common outcome in
> Verilog-XL, with certain command line switches and with certain expressions
> being replicated, Verilog-XL will produce other results. So this behavior
> is not really defined even by the de facto standard.
This archive was generated by hypermail 2b28 : Wed Jul 16 2003 - 17:27:41 PDT