Subject: [sv-bc] sv 3.1 errors in parameter declaration syntax
From: Shalom Bresticker (Shalom.Bresticker@motorola.com)
Date: Wed Jul 09 2003 - 02:53:59 PDT
Hi,
My colleague Rob Slater has pointed out that the SV LRM shows parameter
declarations in module_parameter_port_lists in the module header with
semicolons.
Examples (3.1 LRM):
p. 218, bottom:
interface simple_bus #(parameter AWIDTH = 8, DWIDTH = 8;)
(input bit clk); // Define the interface
p. 223
module ma #( parameter p1 = 1; parameter type p2 = shortint; )
(input logic [p1:0] i, output logic [p1:0] o);
This is a mistake, isn't it?
It was first mentioned in http://www.eda.org/vlog-pp/hm/0227.html .
A correction was voted on in April 2002 (
http://www.eda.org/vlog-pp/hm/0542.html ),
and has entered 1364-2001 as ETF issue #114 (with a minor, transparent, change).
An example of the correct syntax can be seen in section 12.2 of 1364-2001.
-- Shalom Bresticker Shalom.Bresticker@motorola.com Design & Reuse Methodology Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
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