Subject: Re: [sv-bc] Separate Compilation Meeting Monday 6/9/03
From: Randy Misustin (ram@model.com)
Date: Wed Jun 18 2003 - 21:46:50 PDT
Hi Adam,
Adam Krolnik wrote:
> Hi Randy;
>
> On the surface, namespaces look like modules. It may be helpful in
> analyzing
> this to see a comparison between modules and namespaces.
Yeah, this certainly occurred to me many times while putting the
proposal together. The main distinction, in the end, is that namespaces
are a vehicle intended to allow sharing without occupying a place in the
hierarchy. Modules occupy hierarchy. It seems a historical hack that
one might use secondary toplevel modules to achieve this effect in
classic Verilog and, I would imagine, is what led to the use of $root as
a repository for declarations in Superlog/SystemVerilog (which is what
I'm trying to fix with this proposal).
I was trying to provide a scope from which to import symbols. If one
wishes to substitute a module for this usage, then one would presumably
import a hierarchical path rather than the name of a declarative region.
The notion of importing the symbols from one hierarchical region into
another is abhorrent (at least to me). This all led me to want the
target of the import to be something different than anything that exists
today in Verilog.
> You also write that import statements outside a module or scope will
> affect subsequent
> module or interface scopes.
>
> Do import statements only have file scope? Or could one import
> something for the first
> file and have subsequent files obtain the effects of the import?
I didn't give this a lot of thought, but my thinking at the time was
that it would simply affect the next module/macromodule/interface and
not all modules in a file or compilation unit.
> I presume they have file scope. Thus for files with multiple modules
> one import is
> sufficient.
>
> For the import statement, why would it be necessary to say
>
> import Myspace.*;
>
> Other languages (such as Perl) only require reference to the name to
> import all
> the definitions:
>
> use Getopt::Long; # Get all definitions
>
> import Complex; // Get all verilog complex math functions.
I'm not too hung up on ".*". I modeled it somewhat on VHDL ("use
lib.pkg.all;'") but without the addtional keyword.
> Can one import a wire/net declared in the namespace? What does this
> mean? a wire
> that is shared by all modules importing it? What does it mean if you
> import a
> wire but are not in a module scope? in a named scope?
Yeah, I wanted to allow importing of a wire/net. My sense is that the
wire/net/variable "live" in the namespace. Importing simply provides
convenient visibility of these objects in the local scope (an alias?).
-randy.
> Thanks.
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
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