Subject: Re: [sv-bc] RE: [sv-ec] Question: logic & reg - what is the difference?
From: Stephen Williams (steve@icarus.com)
Date: Mon Jun 09 2003 - 19:29:38 PDT
Kevin Said:
> >A "reg" is actually a composite object, it is the combination of a driver
> >and a wire. When you write to it you are assigning to the driver and when
> >you read you get the wire value (the resolution of all the drivers of the
> >wire). "logic" is the (default) type of the driver.
Steven Sharp said:
> I am afraid you are confused here. A reg is not resolved. When you write
> to it, you write to the actual value. When you read from it, you get the
> last value that was written. It works just like a variable in a normal
> programming language.
I agree with Steve here. A reg is a variable in exactly the same sense
as a variable in C. Drivers from reg objects are a consequence of their
use, and *not* their existance. To wit:
reg foo;
wire bar = foo;
wire bel = foo;
Two drivers here, each associated with the continuous assignment. One
might protest that even that is only one driver. In fact, a compiler
may choose here to implement the two drivers as one driver with a fan-
out of 2, but consider this:
reg foo;
reg bar;
wire bat, bell;
assign bat = foo;
assign bat = bar;
assign bell = foo;
The compiler must make two drivers here, lest a single driver from
reg foo would cause a connection between bat and bell, which is not
correct.
So a reg is a variable, plain and simple. The drivers from a reg are
aspects of assignments into nets, and I have the bug reports as proof:-)
(In fact, a vpi_put_value to one of the nets bar or bel in the first
example can further entangle you if you have the wrong model in your
head.)
-- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."
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