Subject: Re: [sv-bc] RE: [sv-ec] Question: logic & reg - what is the difference?
From: Stephen Williams (steve@icarus.com)
Date: Mon Jun 09 2003 - 09:30:34 PDT
stuart@sutherland-hdl.com said:
> I hate to show off my ignorance, but for the sake of a Verilog user,
> and not one who writes tools or parsers, can you explain the
> difference between "reg as an object declaration" and "logic as a
> type"? How does the difference affect tools, the PLI, and most
> importantly the user writing SystemVerilog code?
Given the specific syntax of System Verilog, it doesn't matter, but
the idea is that there is the distinction between variable and net
(the "kind") and there is the orthogonal distinction between logic
and bit and real and etc. (the "type").
Imagine this syntax:
reg logic foo;
wire logic bar;
wire real bat;
The "wire" or "reg" say where the object can be used, and the "logic"
and "real" say what the object type is. In a theoretical orthogonal
type/class arrangement, the kind and type are independent properties
of an object.
SystemVerilog uses different keywords to call out this information
instead of this example syntax arrangement (and doesn't even support
the full matrix) but that is I believe where Jay is coming from.
-- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."
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