Subject: [sv-bc] SystemVerilog 3.1 LRM Passed all Committees
From: Vassilios.Gerousis@Infineon.Com
Date: Fri Apr 25 2003 - 10:13:40 PDT
Dear SV members,
Thanks to your hard work for the past several weeks in building an
excellent LRM that we can be proud to send
To the Accellera Board. We have achieved over 2/3 majority required for us
to approve SystemVerilog 3.1 as an Accellera technical standard.
The chairs and champions have provided sleepless nights to help in the
quality of this LRM based on your large number of feedback. Our LRM editor
Has worked, Stuart Sutherland has worked days and through the nights to meet
the deadline we set.
We will send a detailed voting a summary shortly.
This is truly a remarkable work that majority has voted has yes. As
expected, Cadence is the only company who voted
Against this LRM.
Now the next step for us is get the LRM through Accellera Board
Vote. It will take a month of review by the members.
In the meantime, we will examine the latest LRM and correct mistakes
or typos (nothing else can be touched).
Thanks for everyone who participated through this year and also in
this last several weeks to make this successful work.
Best Regards
Vassilios
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Dr. Vassilios Gerousis
Chief Scientist
Infineon Technologies
DAT CS, MchB
D-81541 Munich
Germany
BalanSt. 73
Telephone: +49-89-234-21342
Fax: +49-89-234-23650
email: Vassilios.Gerousis@infineon.com
Site Map:
http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
<http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73>
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