[sv-bc] SystemVerilog 3.1 draft 6 available for review


Subject: [sv-bc] SystemVerilog 3.1 draft 6 available for review
From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Thu Apr 24 2003 - 12:11:29 PDT


All,

Draft 6 of the SystemVerilog 3.1 LRM is now available to download and
review. The PDF file can be found at:

http://www.sutherland-hdl.com/download/SystemVerilog_3.1_draft6.pdf

This draft highlights the changes between draft 5 and draft 6. In a short
while I will also post a clean version of this draft, with all text marked
to be deleted removed, and colored text changed to black. I will leave the
BNF keywords and tokens as bold-red text, however. The clean version will
be referred to as the "ballot-draft". Hurray!

Stu

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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