Subject: [sv-bc] FW: [sv-ec] Section 19 of Draft - Interfaces
From: David W. Smith (david.smith@synopsys.com)
Date: Thu Apr 24 2003 - 09:19:34 PDT
A question sent to the EC reflector that I think BC may also want to answer.
Regards
David
David W. Smith
Synopsys Scientist
Synopsys, Inc.
Synopsys Technology Park
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Hillsboro, OR 97124
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-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Raghuraman R
Sent: Wednesday, April 23, 2003 11:11 PM
To: sv-ec@eda.org
Subject: [sv-ec] Section 19 of Draft - Interfaces
Hi,
In the module instantiation section, I have this issue.
If we are having a module having a port say
module dummy (A, B, Y)
input [0:3] A;
input B;
output Y;
endmodule
and we want to instantiate the module dummy with only bit of the port A
instantiated, we need something like this
wire wir1,wir2,wir3;
dummy dummy_inst(.A[1](wir1), .B(wir2), .Y(wir3));
Currently the way to do it is
dummy dummy_inst(.A{,wir1,,,},.B(wir2), .Y(wir3));
But for this, we have to know the size of the port, but I think with the
existing information, one should to be able to instantiate and proceed.
Thanks.
Thanks.
-- Regds,Raghuraman R ASIC Texas Instruments (India) Ltd. Phone : +91-80-5099113 http://www.india.ti.com/~raghu
* Think. *
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