Subject: RE: [sv-bc] Assignments in expressions as an atomic operator
From: David W. Smith (david.smith@synopsys.com)
Date: Thu Apr 17 2003 - 09:15:22 PDT
Greetings,
After discussion with Arturo and Dave Rich about this there was agreement
that this had been decided to be removed. LRM-254 has been created and
should be fixed in Draft 5.
Regards
David
-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Jay
Lawrence
Sent: Wednesday, April 16, 2003 5:19 PM
To: sv-bc@eda.org
Cc: David Smith
Subject: [sv-bc] Assignments in expressions as an atomic operator
I know it is very late for this comment but in working on SystemVerilog
related tasks I came across the following in Sections 9.1 and 9.7.
"Execution of each thread can be interrupted between statements at a
semicolon, but a single statement (not a block) containing no user task or
function call shall not be interrupted. This allows atomic test-and-set
using assignment operators in an if statement"
This was discussed at length in one of the face-to-face sv-bc meetings. I
believe it was the one in January. I thought it was agreed that this was a
change to the simulation semantics that was to be removed from the LRM. I
apologize for not catching this early in the meeting minutes or subsequent
review. These little paragraphs can be tricky.
I would ask that an LRM issue be created for this item.
Thanks,
Jay
===================================
Jay Lawrence
Senior Architect
Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================
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