Subject: [sv-bc] RE: ASWG Final Status
From: Vassilios.Gerousis@Infineon.Com
Date: Sat Mar 22 2003 - 00:31:58 PST
Dave,
I want to thank you and the ASWG team for accomplishing this task. I
know that several of you have worked during the night and maybe weekend to
get this accomplished. Your team should be congratulated for this
achievement
The basic goal is to ensure that SVA is line with the rest of
Verilog/SystemVerilog syntax. Your team has achieved consensus on the
results. The semantics concerns will be investigated by the DWG and
hopefully close on all issues, early next week.
Thanks again to everyone on the team and also the people who worked behind
the scene to get this agreement done among all SV committees
representatives.
ASWG TEAM
===========
Dave Rich Leader
Jay Lawrence@cadence.com
Surrendra.Dudani@synopsys.com
Neil.Korpusik@eng.sun.com
bassam@novas.com
johny.srouji@intel.com
Joao.Geada@synopsys.com
Best Regards
Vassilios
-----Original Message-----
From: Dave Rich [mailto:David.Rich@synopsys.com]
Sent: Friday, March 21, 2003 11:56 PM
To: Gerousis Vassilios (CL DAT CS)
Cc: Jay Lawrence; fhaque@cisco.com; Surrendra.Dudani@synopsys.com;
Neil.Korpusik@eng.sun.com; bassam@novas.com; johny.srouji@intel.com;
Joao.Geada@synopsys.com; Arturo.Salz@synopsys.com;
Stephen.Meier@synopsys.com; Jayant Nagda
Subject: ASWG Final Status
Vassilios,
The ACWG has reached an agreement on all open issues, as indicated in
the attached document. Jay Lawrence is updating the BNF document to
reflect the decisions made by our committee. That will go through one
quick sanity review via email today, so we will have a document ready
for you on Monday.
Dave
-- Dave Rich Principal Engineer, CAE, VTG Tel: 650-584-4026 Cell: 510-589-2625 DaveR@Synopsys.com
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